Prevention of neighboring plane disturb in non-volatile memory
US10141064B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for the prevention and detection of inter-plane disturbs in a memory circuit, where, when concurrently performing memory operations on multiple planes, a defect in one plane can feed back through a common supply node and adversely affect memory operations in another node. To isolate such defects to plane in which the occur, the memory supplies the elements, such as a word line, of different planes from a common supply node through a uni-directional circuit element, such as a diode. In this way, if the voltage on an element in an array gets pulled up to an elevated voltage though a defect, this elevated voltage is stopped from flowing back to the common supply node. Additionally, by comparing the voltage levels on either side of the uni-directional circuit element, it can be determined whether such a defect is present in an array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.