FinFET device with wrapped-around epitaxial structure and manufacturing method thereof
US10141231B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Aug 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A method includes forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region; forming a gate stack engaging each fin at the respective channel region; depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins; and performing an etching process to the one or more dielectric layers. The etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surface of the gate stack still being covered by the one or more dielectric layers. The method further includes growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.