Semiconductor power device including adjacent thermal substrate for thermal impedance reduction
US10141238B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor power device including a base plate, a semiconductor power die disposed on the base plate, an input lead by way the semiconductor power die receives an input signal, an output lead by way an output signal generated by the semiconductor power die is sent to another device, and at least one thermal substrate disposed on the base plate adjacent to the semiconductor power die, wherein a set of electrodes of the semiconductor power die are thermally and electrically coupled to a metallization layer on the thermal substrate. The thermal substrate may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The thermal substrate produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.