Methods of manufacturing semiconductor packages
US10141286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.