Method for producing a layer structure as a buffer layer of a semiconductor component and layer structure as a buffer layer of a semiconductor component
US10147601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2015 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
What is specified is a method for producing a layer structure (10) as a buffer layer of a semiconductor component, said method comprising the following steps: a) provision of a carrier (1), which has a silicon surface (1a), b) deposition of a first layer sequence (2), which comprises a seeding layer (21) containing aluminum and nitrogen, on the silicon surface (1a) of the carrier (1) along a stacking direction (H) running perpendicular to a main plane of extent of the carrier (1), c) three-dimensional growth of a 3D-GaN layer (3), which is formed with gallium nitride, on a top surface (2a) of the first layer sequence (2) which is remote from the silicon surface (1a), d) two-dimensional growth of a 2D-GaN layer (4), which is formed with gallium nitride, on the outer surfaces (3a) of the 3D-GaN layer (3) which are remote from the silicon surface (1a).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.