Method of fabricating a transistor with reduced hot carrier injection effects
US10147800B2 · kind B2 · utility
1Cited by
1References
14Claims
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Assignee
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Key dates
| Filing date | Feb 19, 2016 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Mar 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.