Method and apparatus for determining a timing adjustment of output to a host memory controller
US10152370B2 · kind B2 · utility
5Cited by
21References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2015 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Dec 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method and apparatus for determining a timing adjustment of output to a host memory controller in a first memory module coupled to a host memory controller and a second memory module over a bus. A determination is made of a timing adjustment based on at least one component in at least one of the first memory module and the second memory module. A timing of output to the host memory controller is adjusted based on the determined timing adjustment to match a timing of output at the second memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.