Inventor · Livermore, CA, US

Bill Nale

63Patents
9h-index
52Co-inventors
81Inventor score

Filing activity: Sep 7, 2004 → Sep 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9342453B2 Memory channel that supports near memory and far memory access Emerging Cross-Sectional Technologies 77 Active
US9619408B2 Memory channel that supports near memory and far memory access Emerging Cross-Sectional Technologies 30 Active
US7454586B2 Memory device commands Physics 25 Expired
US10241943B2 Memory channel that supports near memory and far memory access Emerging Cross-Sectional Technologies 18 Active
US10282323B2 Memory channel that supports near memory and far memory access Emerging Cross-Sectional Technologies 14 Active
US10282322B2 Memory channel that supports near memory and far memory access Emerging Cross-Sectional Technologies 14 Active
US10950288B2 Refresh command control for host assist of row hammer mitigation Physics 13 Active
US10496473B2 Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) Physics 11 Active
US10636476B2 Row hammer mitigation with randomization of target row selection Physics 10 Active
US11282561B2 Refresh command control for host assist of row hammer mitigation Physics 8 Active
US10146711B2 Techniques to access or operate a dual in-line memory module via multiple data channels Emerging Cross-Sectional Technologies 8 Active
US10872011B2 Internal error checking and correction (ECC) with extra system bits Physics 7 Active
US9811420B2 Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) Physics 6 Active
US11688452B2 Refresh command control for host assist of row hammer mitigation Physics 6 Active
US9658963B2 Speculative reads in buffered memory Emerging Cross-Sectional Technologies 6 Active
US9990246B2 Memory system Physics 5 Active
US10152370B2 Method and apparatus for determining a timing adjustment of output to a host memory controller Physics 5 Active
US7188208B2 Side-by-side inverted memory address and command buses Emerging Cross-Sectional Technologies 4 Expired
US10061719B2 Packed write completions Physics 4 Active
US9740646B2 Early identification in transactional buffered memory Physics 4 Active
US9852021B2 Method and apparatus for encoding registers in a memory module Physics 3 Active
US10747605B2 Method and apparatus for providing a host memory controller write credits for write commands Physics 2 Active
US9251874B2 Memory interface signal reduction Physics 2 Active
US10839887B2 Applying chip select for memory device identification and power management control Emerging Cross-Sectional Technologies 2 Active
US10592445B2 Techniques to access or operate a dual in-line memory module via multiple data channels Emerging Cross-Sectional Technologies 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.