Instruction and logic for cache control operations
US10152421B2 · kind B2 · utility
1Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Jan 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.