In-memory computational device with bit line processors
US10153042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Jul 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device includes bit line processors, multiplexers and a decoder. Each bit line processor includes a bit line of memory cells and each cell stores one bit of a data word. A column of bit line processors stores the bits of the data word. Each multiplexer connects a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors. The decoder activates at least two word lines of the bit line processor of the first row and a word line in the bit line processor in the second row and enables a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row to be written into the cell in the bit line processor in the second row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.