GSI Technology Inc.
🏢 View company profile →128Patents
125Active
128Granted
60Portfolio score
Filing activity: Oct 15, 2004 → Feb 18, 2024 · 2 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10153042B2 | In-memory computational device with bit line processors | Physics | 37 | Active |
| US9053768B2 | Systems and methods of pipelined output latching involving synchronous memory arrays | Physics | 32 | Active |
| US9240229B1 | Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode | Physics | 30 | Active |
| US9558812B2 | SRAM multi-cell operations | Physics | 29 | Active |
| US9356611B1 | Systems and methods involving phase detection with adaptive locking/detection features | Electricity | 29 | Active |
| US10249362B2 | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations | Physics | 29 | Active |
| US8693236B2 | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features | Physics | 28 | Active |
| US9692429B1 | Systems and methods involving fast-acquisition lock features associated with phase locked loop circuitry | Electricity | 28 | Active |
| US9679631B2 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Physics | 27 | Active |
| US9494647B1 | Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects | Physics | 27 | Active |
| US9385032B2 | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation | Emerging Cross-Sectional Technologies | 27 | Active |
| US9159391B1 | Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features | Physics | 27 | Active |
| US9413295B1 | Systems and methods of phase frequency detection with clock edge overriding reset, extending detection range, improvement of cycle slipping and/or other features | Electricity | 27 | Active |
| US8575982B1 | Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines | Electricity | 27 | Active |
| US8400200B1 | Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines | Electricity | 26 | Active |
| US8593860B2 | Systems and methods of sectioned bit line memory arrays | Physics | 26 | Active |
| US9094025B1 | Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects | Electricity | 26 | Active |
| US9384822B2 | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features | Emerging Cross-Sectional Technologies | 26 | Active |
| US9613684B2 | Systems and methods involving propagating read and write address and data through multi-bank memory circuitry | Physics | 26 | Active |
| US9135986B2 | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features | Physics | 25 | Active |
| US9853633B1 | Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry | Electricity | 25 | Active |
| US9196324B2 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Physics | 25 | Active |
| US9431079B1 | Systems and methods of memory and memory operation involving input latching, self-timing and/or other features | Physics | 25 | Active |
| US10192592B2 | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features | Emerging Cross-Sectional Technologies | 25 | Active |
| US9859902B2 | Systems and method involving fast-acquisition lock features associated with phase locked loop circuitry | Electricity | 25 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.