Chip package and method for forming the same
US10153237B2 · kind B2 · utility
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22Claims
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Assignee
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Key dates
| Filing date | Mar 16, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Mar 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.