Po-Han Lee
26Patents
3h-index
33Co-inventors
59Inventor score
Filing activity: Jun 13, 2008 → May 5, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8952519B2 | Chip package and fabrication method thereof | Electricity | 6 | Active |
| US8823179B2 | Electronic device package and method for fabricating the same | Electricity | 4 | Active |
| US8872196B2 | Chip package | Electricity | 3 | Active |
| US10446504B2 | Chip package and method for forming the same | Electricity | 2 | Active |
| US8432032B2 | Chip package and fabrication method thereof | Electricity | 2 | Active |
| US9196571B2 | Chip device packages and fabrication methods thereof | Electricity | 2 | Active |
| US8319347B2 | Electronic device package and fabrication method thereof | Electricity | 1 | Active |
| US9947716B2 | Chip package and manufacturing method thereof | Electricity | 1 | Active |
| US10424540B2 | Chip package and method for forming the same | Electricity | 1 | Active |
| US9640683B2 | Electrical contact structure with a redistribution layer connected to a stud | Electricity | 1 | Active |
| US9780251B2 | Semiconductor structure and manufacturing method thereof | Electricity | 0 | Active |
| US11476293B2 | Manufacturing method of chip package | Electricity | 0 | Active |
| US9269837B2 | Chip package and method of manufacturing the same | Emerging Cross-Sectional Technologies | 0 | Active |
| US11355659B2 | Chip package and manufacturing method thereof | Electricity | 0 | Active |
| US10153237B2 | Chip package and method for forming the same | Electricity | 0 | Active |
| US9214579B2 | Electrical contact structure with a redistribution layer connected to a stud | Electricity | 0 | Active |
| US10096635B2 | Semiconductor structure and manufacturing method thereof | Electricity | 0 | Active |
| US9305842B2 | Fabrication methods of chip device packages | Electricity | 0 | Active |
| US11387201B2 | Chip package and manufacturing method thereof | Electricity | 0 | Active |
| US11038077B2 | Chip package and manufacturing method thereof | Electricity | 0 | Active |
| US11340679B1 | Uninterruptible power system testing method | Physics | 0 | Active |
| US9406818B2 | Chip package and method of manufacturing the same | Emerging Cross-Sectional Technologies | 0 | Active |
| US11310904B2 | Chip package and power module | Electricity | 0 | Active |
| US10879530B2 | Anode material of nano-silicon having multilayer-graphene as carrier and coated with silicon suboxide and with amorphous carbon layer and method for fabricating the same | Emerging Cross-Sectional Technologies | 0 | Active |
| US9875912B2 | Chip package and manufacturing method thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.