Memory device and method for manufacturing same
US10153296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Jul 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate and a stacked body arranged along a first direction. The stacked body includes electrode films. A configuration of an end portion in a second direction of the stacked body is a staircase configuration. Steps corresponding to the electrode films are formed in the staircase configuration. A first distance between a first step and an end edge of the stacked body in the second direction is shorter than a second distance between a second step and the end edge in the second direction. The first step is positioned at an end portion in a third direction of the stacked body. The second step is positioned at a central portion in the third direction of the stacked body. The first and second steps correspond to two of the electrode films positioned at the same level when counting along the first direction from the substrate side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.