Method for managing the operation of a low-complexity synchronous retention flip-flop circuit, and corresponding circuit
US10153754B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 16, 2017 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Mar 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.