Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
US10153769B2 · kind B2 · utility
1Cited by
12References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 13, 2015 |
| Grant date | Dec 11, 2018 |
| Priority date | — |
| Expiry date | Sep 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.