Inter-poly connection for parasitic capacitor and die size improvement
US10155656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0792
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.