Method for reviewing defects
US10156526B1 · kind B1 · utility
1Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.