Device and method for robustness verification
US10156609B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | May 23, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jul 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.