Methods and devices for reducing array size and complexity in automata processors
US10157165B2 · kind B2 · utility
3Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | May 27, 2016 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/24059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position encoded pattern to a second position encoded pattern to identify a second data pattern within the first data pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.