Data output for high frequency domain
US10157648B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jul 18, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02W10/37
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.