Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory cells per bit
US10157669B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2013 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Apr 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.