Method of manufacturing a semiconductor structure
US10157741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70533
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing a semiconductor structure includes providing a first lot including a plurality of first wafers and a second lot including a plurality of second wafers; deriving a first processing time for processing the first lot; deriving a second processing time for processing the second lot; deriving a processing time difference between the first processing time and the second processing time; loading a first mask on a mask stage; processing the first lot on a wafer stage; removing the first mask from the mask stage; loading a second mask on the mask stage; and processing the second lot on the wafer stage, wherein a time interval between accomplishment of the processing of the first lot and beginning of the processing of the second lot is substantially greater than or equal to the processing time difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.