Semiconductor packaging structure and process
US10157772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.