Interconnect structure and method
US10157867B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: an interconnect structure over a substrate, the interconnect structure including a first metal line and a second metal line, the first metal line longer than the second metal line; a surface dielectric layer over the interconnect structure; a plurality of first vias in the surface dielectric layer; a first bonding pad in the surface dielectric layer, where the first bonding pad is connected to a first end of the first metal line through the first vias; a plurality of second vias in the surface dielectric layer; a second bonding pad in the surface dielectric layer, the second bonding pad and the first bonding pad separate from each other, where the second bonding pad is connected to a second end of the first metal line through the second vias; and a third bonding pad in the surface dielectric layer, where the third bonding pad is connect to the second metal line through a third via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.