Ming-Fa Chen
426Patents
21h-index
94Co-inventors
93Inventor score
Filing activity: Sep 5, 1997 → Jun 24, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8803292B2 | Through-substrate vias and methods for forming the same | Electricity | 368 | Active |
| US9859254B1 | Semiconductor structure and a manufacturing method thereof | Electricity | 261 | Active |
| US8158456B2 | Method of forming stacked dies | Electricity | 123 | Active |
| US9899355B2 | Three-dimensional integrated circuit structure | Electricity | 61 | Active |
| US9698081B2 | 3D chip-on-wafer-on-substrate structure with via last process | Electricity | 60 | Active |
| US10510650B2 | Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias | Electricity | 54 | Active |
| US9524959B1 | System on integrated chips and methods of forming same | Electricity | 49 | Active |
| US10522449B2 | Packages with Si-substrate-free interposer and method forming same | Electricity | 48 | Active |
| US10541228B2 | Packages formed using RDL-last process | Electricity | 45 | Active |
| US8378480B2 | Dummy wafers in 3DIC package assemblies | Electricity | 44 | Active |
| US10541227B2 | System on integrated chips and methods of forming same | Electricity | 43 | Active |
| US10373885B2 | 3D stacked-chip package | Electricity | 43 | Active |
| US8174124B2 | Dummy pattern in wafer backside routing | Electricity | 31 | Active |
| US10510629B2 | Integrated circuit package and method of forming same | Electricity | 28 | Active |
| US8049327B2 | Through-silicon via with scalloped sidewalls | Electricity | 27 | Active |
| US5989754A | Photomask arrangement protecting reticle patterns from electrostatic discharge damage (ESD) | Physics | 27 | Expired |
| US8501587B2 | Stacked integrated chips and methods of fabrication thereof | Electricity | 26 | Active |
| US9666520B2 | 3D stacked-chip package | Electricity | 22 | Active |
| US8053902B2 | Isolation structure for protecting dielectric layers from degradation | Electricity | 21 | Active |
| US7910473B2 | Through-silicon via with air gap | Electricity | 21 | Active |
| US8791549B2 | Wafer backside interconnect structure connected to TSVs | Electricity | 21 | Active |
| US8362591B2 | Integrated circuits and methods of forming the same | Electricity | 19 | Active |
| US10157867B1 | Interconnect structure and method | Electricity | 18 | Active |
| US8399354B2 | Through-silicon via with low-K dielectric liner | Electricity | 17 | Active |
| US9142533B2 | Substrate interconnections having different sizes | Electricity | 16 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.