Semiconductor package including bump
US10157873B1 · kind B1 · utility
1Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Sep 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor chip having a pad which is exposed through a passivation layer, a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad. The semiconductor chip also has a solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.