Integrated fan-out packages and methods of forming the same
US10157888B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jul 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19102
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.