Inventor · Pingzhen District, TW

Po-Hao Tsai

228Patents
13h-index
86Co-inventors
89Inventor score

Filing activity: Jun 28, 2002 → May 15, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9048222B2 Method of fabricating interconnect structure for package-on-package devices Electricity 971 Active
US8877554B2 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices Electricity 600 Active
US8778738B1 Packaged semiconductor devices and packaging devices and methods Electricity 587 Active
US8952544B2 Semiconductor device and manufacturing method thereof Electricity 38 Active
US9111914B2 Fan out package, semiconductor device and manufacturing method thereof Electricity 37 Active
US9159678B2 Semiconductor device and manufacturing method thereof Electricity 35 Active
US10170341B1 Release film as isolation film in package Electricity 27 Active
US9460987B2 Interconnect structure for package-on-package devices and a method of fabricating Electricity 19 Active
US9425121B2 Integrated fan-out structure with guiding trenches in buffer layer Electricity 19 Active
US9252065B2 Mechanisms for forming package structure Electricity 17 Active
US9543170B2 Semiconductor packages and methods of forming the same Electricity 16 Active
US8455995B2 TSVs with different sizes in interposers for bonding dies Electricity 15 Active
US10157888B1 Integrated fan-out packages and methods of forming the same Electricity 13 Active
US9842826B2 Semiconductor device and method of manufacture Electricity 13 Active
US10269778B2 Package on package (PoP) bonding structures Electricity 13 Active
US9368438B2 Package on package (PoP) bonding structures Electricity 13 Active
US9583420B2 Semiconductor device and method of manufactures Electricity 13 Active
US9508666B2 Packaging structures and methods with a metal pillar Electricity 12 Active
US9553059B2 Backside redistribution layer (RDL) structure Electricity 12 Active
US9922903B2 Interconnect structure for package-on-package devices and a method of fabricating Electricity 11 Active
US8664760B2 Connector design for packaging integrated circuits Electricity 10 Active
US9219016B2 Structure design for 3DIC testing Electricity 10 Active
US9355977B2 Bump structures for semiconductor package Electricity 10 Active
US8922004B2 Copper bump structures having sidewall protection layers Electricity 9 Active
US10103125B2 Chip package structure and method for forming the same Electricity 8 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.