Nanowire device with reduced parasitics

US10157992B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Mustafa Badaroglu · Kessel-Lo, BE
• Vladimir Machkaoutsan · Leuven, BE
• Stanley Seungchul Song · San Diego, US
• Jeffrey Junhao Xu · San Diego, US
• Matthew Michael Nowak · San Diego, US
• Choh Fei Yeap · San Diego, US

Key dates

• Filing date: Dec 28, 2015
• Grant date: Dec 18, 2018
• Expiry date: Dec 28, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/667
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.