Low-K dielectric sidewall spacer treatment
US10158000B2 · kind B2 · utility
7Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for fabricating a semiconductor structure including sidewall spacers. An example semiconductor structure includes: a gate structure, a first sidewall spacer, and a second sidewall spacer. The gate structure is formed over a substrate. The first sidewall spacer is adjacent to the gate structure, a top part of the first sidewall spacer including a first dielectric material, a bottom part of the first sidewall spacer including a second dielectric material. The second sidewall spacer is adjacent to the first sidewall spacer, the second sidewall spacer including a third dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.