Managing backup of logical-to-physical translation information to control boot-time and write amplification
US10162561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jan 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a processor. The interface is configured to communicate with a non-volatile memory. The processor is configured to hold a translation table that maps between logical addresses and respective physical addresses in the non-volatile memory, to back-up to the non-volatile memory a baseline version of the translation table in one or more bulks, to additionally back-up to the non-volatile memory one or more incremental updates, which specify changes relative to the baseline version of the translation table caused by subsequent storage operations, to determine a maximal number of the incremental updates that, when recovered together with the baseline version from the non-volatile memory and replayed in the processor, meets a target recovery time of the translation table, and to set a number of the backed-up incremental updates to not exceed the maximal number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.