Opportunistic increase of ways in memory-side cache
US10162758B2 · kind B2 · utility
9Cited by
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23Claims
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Key dates
| Filing date | Dec 9, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.