Integrated circuit retiming with selective modeling of flip-flop secondary signals
US10162918B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Apr 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.