Hybrid clock gating methodology for high performance cores
US10162922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | May 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.