Kailash Digari
12Patents
3h-index
8Co-inventors
49Inventor score
Filing activity: Jun 10, 2003 → Apr 12, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9396790B1 | Multi-supply dual port register file | Physics | 37 | Active |
| US6864714B2 | PLDs providing reduced delays in cascade chain circuits | Electricity | 19 | Expired |
| US8112466B2 | Field programmable gate array | Physics | 15 | Active |
| US7755387B2 | FPGA having a direct routing structure | Electricity | 3 | Active |
| US7414433B2 | Interconnect structure enabling indirect routing in programmable logic | Electricity | 1 | Active |
| US10430302B2 | Data retention with data migration | Emerging Cross-Sectional Technologies | 1 | Active |
| US10331532B2 | Periodic non-intrusive diagnosis of lockstep systems | Physics | 1 | Active |
| US7755388B2 | Interconnect structure enabling indirect routing in programmable logic | Electricity | 1 | Active |
| US7307452B2 | Interconnect structure enabling indirect routing in programmable logic | Electricity | 0 | Expired |
| US7961004B2 | FPGA having a direct routing structure | Electricity | 0 | Active |
| US7750673B2 | Interconnect structure and method in programmable devices | Electricity | 0 | Expired |
| US10162922B2 | Hybrid clock gating methodology for high performance cores | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.