Memory array having disturb detector and write assistor
US10163477B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.