Memory device and fabrication method thereof
US10163494B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.