Ren-Fen Tsui
26Patents
3h-index
17Co-inventors
60Inventor score
Filing activity: Sep 13, 2004 → Jan 31, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10297602B2 | Implantations for forming source/drain regions of different transistors | Electricity | 6 | Active |
| US7705464B2 | Connection structure for semiconductor devices | Electricity | 4 | Active |
| US9871046B2 | SRAM circuits with aligned gate electrodes | Electricity | 3 | Active |
| US10269704B2 | Semiconductor device and method | Electricity | 3 | Active |
| US10373879B2 | Semiconductor device with contracted isolation feature and formation method thereof | Electricity | 2 | Active |
| US10332896B2 | SRAM circuits with aligned gate electrodes | Electricity | 2 | Active |
| US9978680B2 | Semiconductor device and method | Electricity | 1 | Active |
| US11037934B2 | SRAM circuits with aligned gate electrodes | Electricity | 1 | Active |
| US9666587B1 | Semiconductor device and method | Electricity | 1 | Active |
| US11145660B2 | Dual-port SRAM cell structure | Electricity | 1 | Active |
| US9805815B1 | Electrical fuse bit cell and mask set | Electricity | 1 | Active |
| US10811321B2 | Semiconductor device with contracted isolation feature | Electricity | 0 | Active |
| US10685967B2 | Implantations for forming source/drain regions of different transistors | Electricity | 0 | Active |
| US12414281B2 | Implantations for forming source/drain regions of different transistors | Electricity | 0 | Active |
| US11532554B2 | Interconnect device and method | Electricity | 0 | Active |
| US10930590B1 | Interconnect device and method | Electricity | 0 | Active |
| US11605637B2 | SRAM circuits with aligned gate electrodes | Electricity | 0 | Active |
| US10847457B2 | Semiconductor device and method | Electricity | 0 | Active |
| US12033940B2 | Semiconductor device and method | Electricity | 0 | Active |
| US11251091B2 | Semiconductor device with contracted isolation feature | Electricity | 0 | Active |
| US10163494B1 | Memory device and fabrication method thereof | Physics | 0 | Active |
| US11527540B2 | Implantations for forming source/drain regions of different transistors | Electricity | 0 | Active |
| US11189340B1 | Circuit in memory device for parasitic resistance reduction | Electricity | 0 | Active |
| US12324222B2 | Semiconductor device with contracted isolation feature | Electricity | 0 | Active |
| US11895819B2 | Implantations for forming source/drain regions of different transistors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.