Selective performance level modes of operation in a non-volatile memory
US10163502B2 · kind B2 · utility
1Cited by
5References
22Claims
0Family size
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Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.