Gate isolation plugs structure and method
US10163640B1 · kind B1 · utility
11Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.