System, apparatus, and method for embedding a 3D component with an interconnect structure
US10163687B2 · kind B2 · utility
2Cited by
27References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Nov 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.