MOS devices with thinned gate spacers and methods of thinning the gate spacers
US10163727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jan 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.