Semiconductor package with improved signal stability and method of manufacturing the same
US10163746B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jan 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and manufacturing method thereof includes a chip member installed on an upper surface, a lower surface, or both of a substrate. The semiconductor package and manufacturing method thereof also include a mold part stacked embedding the chip member, a connection member disposed at a center portion of the mold part, and a solder part formed on a portion of the connection member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.