Integrated fan-out package, redistribution circuit structure, and method of fabricating the same
US10163832B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Oct 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A redistribution circuit structure electrically connected to a die underneath is provided. The redistribution circuit structure includes a dielectric layer and a conductive layer. The dielectric layer partially covers the die, so that a conductive pillar of the die is exposed by the dielectric layer. The conductive layer is disposed over the dielectric layer and electrically connected to the die by the conductive pillar. The conductive layer includes a multilayer structure, wherein an average grain size of one layer of the multilayer structure is less than or equal to 2 μm. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.