Patent · US Active

Semiconductor packages and manufacturing methods thereof

US10163858B1 · kind B1 · utility

9Cited by

10References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Zi-Jheng Liu · Taoyuan, TW
Chen-Cheng Kuo · Taipei, TW
Hung-Jui Kuo · Hsinchu, TW

Key dates

Filing date	Oct 26, 2017
Grant date	Dec 25, 2018
Priority date	—
Expiry date	Oct 26, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18162
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Semiconductor packages and manufacturing methods thereof are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.