Inventor · Hsinchu, TW

Hung-Jui Kuo

350Patents
10h-index
120Co-inventors
83Inventor score

Filing activity: Sep 7, 1999 → May 6, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9899248B2 Method of forming semiconductor packages having through package vias Electricity 64 Active
US9859206B2 Photoactive compound gradient photoresist Electricity 57 Active
US8754508B2 Structure to increase resistance to electromigration Electricity 47 Active
US10622321B2 Semiconductor structures and methods of forming the same Electricity 44 Active
US10490521B2 Advanced structure for info wafer warpage reduction Electricity 38 Active
US9318429B2 Integrated structure in wafer level package Electricity 25 Active
US9793230B1 Semiconductor structure and method of forming Electricity 18 Active
US9659805B2 Fan-out interconnect structure and methods forming the same Electricity 15 Active
US6210841A Approach to increase the resolution of dense line/space patterns for 0.18 micron and below design rules using attenuating phase shifting masks Physics 12 Expired
US9502360B2 Stress compensation layer for 3D packaging Electricity 10 Active
US10163858B1 Semiconductor packages and manufacturing methods thereof Electricity 9 Active
US10276543B1 Semicondcutor device package and method of forming semicondcutor device package Electricity 8 Active
US10361122B1 Processes for reducing leakage and improving adhesion Electricity 8 Active
US10304700B2 Semiconductor device and method Electricity 7 Active
US10049894B2 Package structures and methods for forming the same Electricity 7 Active
US10872864B2 Semiconductor package and method Electricity 6 Active
US11289396B2 Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region Electricity 5 Active
US10861710B2 Methods of manufacturing semiconductor devices Electricity 5 Active
US10340206B2 Dense redistribution layers in semiconductor packages and methods of forming the same Electricity 5 Active
US11322450B2 Chip package and method of forming the same Electricity 5 Active
US10510645B2 Planarizing RDLs in RDL-first processes through CMP process Electricity 5 Active
US8791579B2 Adjusting sizes of connectors of package components Electricity 5 Active
US10276402B2 Semiconductor package and manufacturing process thereof Electricity 5 Active
US10297544B2 Integrated fan-out package and method of fabricating the same Electricity 5 Active
US10964591B2 Processes for reducing leakage and improving adhesion Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.