Three-layer stacked image sensor
US10163946B2 · kind B2 · utility
4Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Apr 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor may include a lower device that includes logic transistors, an intermediate device that is formed over the lower device and includes a Correlated Double Sampling (CDS) circuit and a capacitor, and an upper device that is formed over the intermediate device and includes a photodiode, a floating diffusion region, and a transfer gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.