Metal landing method for RRAM technology
US10163981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Feb 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.