Formation method of semiconductor device structure with cap element
US10164013B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Aug 29, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Aug 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Formation methods of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a source/drain structure adjacent to the gate stack. The method also includes forming a cap element over the source/drain structure. The cap element has a top surface and a side surface, and a width ratio of the top surface to the side surface of the cap element is in a range from about 0.125 to about 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.